It is common for high voltage transistors, high voltage diodes, and high voltage circuits to be formed on same integrated circuit chip as low voltage circuits. They may be used to form buck circuits to step high voltage down to low voltage, boost circuits, to step low voltage up to high voltage, half bridge circuits to rectify AC signals, or for other high voltage logic applications. Frequently they are used for high power applications.
There are two primary methods of adding high voltage capability to an integrated circuit (IC) manufacturing flow. One method is to provide one thickness gate dielectric for core logic and for high voltage transistors to provide a second, thicker gate dielectric and also high voltage transistor patterning and implantation steps. This method adds significant cost to the integrated circuit process flow.
A second method is to form extended drain transistors which avoid the need for two gate dielectric thicknesses. Extended drain transistors (DEMOS) are designed to drop sufficient voltage across an extended drain depletion region so that a core transistor with core gate dielectric may be used to switch the current from a high voltage source.
DEMOS transistors with a charged balanced extended drain are described, e.g. in US 2008-0246086 A1, to Korec, et. al. which is incorporated herein by reference. The charge balanced extended drain enables a reduced area extended drain which reduces manufacturing cost.
Also described in the above mentioned patent publication are NMOS high voltage transistors which use the substrate as one of the transistor nodes. Using the substrate for the current path significantly improves the performance of high power transistors by lowering series resistance, Rsd. For RF applications, NMOS transistors are preferred for speed and are commonly built on p-type substrates. P-type substrates typically are 2 to 3 times more resistive than n-type substrates.
FIG. 1 from the above mentioned patent publication illustrates a high performance, high voltage, charge balanced, drain extended, NMOS power transistor (CBDENMOS) built in an isolated pwell 16 on n-type substrate, 12. The n-type substrate 12 forms the high voltage transistor drain 11 of the CBDENMOS transistor. When a high voltage is placed on the drain, 11, a depletion region forms between the N-substrate, 12, and the p-well 16, between the n-sinker 14 and the p-well 16, and between the NLDD, 20 and the p-well, 16. The drain extension, 20 fully depletes so that sufficient high voltage is dropped between the n-sinker, 14, and the transistor gate 31 to protect the gate dielectric, 36. The gate shield, 28, is shorted to the source 18 and the substrate contact 26. Dielectric layer 34 electrically isolates the gate shield from the gate 31 and the extension region 20. The gate shield 28 overlies the drain extension region, 20, providing a charge balanced condition which enables a higher voltage to be dropped across a shorter length LDD, 20. When the gate 31 is turned on, a channel is formed, and current flows from the drain, 11, through the n-sinker, 14, through the drain extension, 20, through the channel, through the source diffusion, 18 and out the source contact metallization, 29. The n-substrate drain terminal 11 and n-sinker 14 provide a lower resistance path than power transistors with both a topside source and a topside drain. The bottom side substrate drain in CBDENMOS transistor 10 reduces Rsd and enhances the transistor performance especially in high power and high frequency applications.